tests - Add first interrupt tests
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tests/test_cpu_interrupts.cpp
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68
tests/test_cpu_interrupts.cpp
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#include "doctest.h"
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#include "cpu/cpu.h"
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#include "memory/ram.h"
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TEST_CASE("EI followed by DI should not trigger interrupt")
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{
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u8 test_ram[] = {
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0xFB, // EI
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0xF3, // DI
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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};
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RAM r(test_ram, 0x20, true);
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Cpu cpu(&r);
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cpu.state.IE = 0x1F; // Enable all types of interrupts
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cpu.state.IF = 0x1F; // All interrupts pending
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CHECK(cpu.state.PC == 0x0);
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CHECK(cpu.state.IME == IME_OFF);
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cpu.step();
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CHECK(cpu.state.PC == 0x1);
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CHECK(cpu.state.IME == IME_SCHEDULED);
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cpu.step();
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CHECK(cpu.state.PC == 0x2);
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CHECK(cpu.state.IME == IME_OFF);
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cpu.step();
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CHECK(cpu.state.PC == 0x3);
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CHECK(cpu.state.IME == IME_OFF);
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}
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TEST_CASE("interrupt triggers call to correct ISR")
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{
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RAM r(0x100);
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Cpu cpu(&r);
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cpu.state.IME = IME_ON;
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cpu.state.IE = INT_MASK;
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InterruptType it;
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u8 expected_pc;
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SUBCASE("VBlank") { it = INT_VBlank; expected_pc = 0x40; }
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SUBCASE("LCDSTAT") { it = INT_LCDSTAT; expected_pc = 0x48; }
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SUBCASE("Timer") { it = INT_Timer; expected_pc = 0x50; }
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SUBCASE("Serial") { it = INT_Serial; expected_pc = 0x58; }
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SUBCASE("Joypad") { it = INT_Joypad; expected_pc = 0x60; }
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cpu.signalInterrupt(it);
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CHECK(cpu.state.IF == it);
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cpu.step();
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CHECK(cpu.state.IF == 0);
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CHECK(cpu.state.PC == expected_pc);
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CHECK(cpu.state.IME == IME_OFF);
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}
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