Fix build errors.
This commit is contained in:
parent
8019408684
commit
8d063c08ca
4 changed files with 106 additions and 59 deletions
5
Makeconf
5
Makeconf
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@ -1,5 +1,6 @@
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modules := test \
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memory/bus \
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memory/ram
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memory/bus \
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memory/ram \
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cpu/decoder
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CXX_FLAGS := -I $(CURDIR)
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14
cpu/cpu.h
14
cpu/cpu.h
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@ -12,11 +12,6 @@ enum Flags {
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F_CARRY = 0x1,
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};
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union Register_pair {
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struct { u8 hi; u8 lo; }
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u16 hilo;
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};
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struct Cpu_state {
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// Registers
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union {
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@ -50,11 +45,14 @@ private:
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typedef u8 opcode_t;
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private:
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u8 readPC();
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u8 readPC8();
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u16 readPC16();
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void pushStack(u8 data);
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u8 popStack();
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void pushStack8(u8 data);
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u8 popStack8();
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void pushStack16(u16 data);
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u16 popStack16();
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public:
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Cpu();
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142
cpu/decoder.cpp
142
cpu/decoder.cpp
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@ -1,4 +1,5 @@
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#include "cpu/cpu.h"
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#include "memory/mem_device.h"
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u8 Cpu::readPC8()
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{
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@ -14,26 +15,26 @@ u16 Cpu::readPC16()
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return data;
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}
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void pushStack8(u8 data)
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void Cpu::pushStack8(u8 data)
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{
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bus->write8(state.SP, data);
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state.SP--;
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}
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u8 popStack8()
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u8 Cpu::popStack8()
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{
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u8 data = bus->read8(state.SP);
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state.SP++;
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return data;
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}
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void pushStack16(u16 data)
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void Cpu::pushStack16(u16 data)
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{
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bus->write16(state.SP,data);
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state.SP-=2;
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}
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void popStack16()
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u16 Cpu::popStack16()
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{
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u16 data = bus->read16(state.SP);
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state.SP+=2;
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@ -42,67 +43,114 @@ void popStack16()
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void Cpu::step()
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{
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opcode_t op = readPC();
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opcode_t op = readPC8();
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int mcycles = 1;
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switch(op) {
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0x00: // NOP
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(void) ;;
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case 0x00: break; // NOP
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0x01: // LD BC, n16
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state.BC = readPC16(); mcycles = 12;;
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0x11: // LD DE, n16
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state.DE = readPC16(); mcycles = 12;;
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0x21: // LD HL, n16
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state.HL = readPC16(); mcycles = 12;;
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0x31: // LD SP, n16
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state.SP = readPC16(); mcycles = 12;;
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case 0x01: // LD BC, n16
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state.BC = readPC16(); mcycles = 12; break;
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case 0x11: // LD DE, n16
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state.DE = readPC16(); mcycles = 12; break;
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case 0x21: // LD HL, n16
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state.HL = readPC16(); mcycles = 12; break;
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case 0x31: // LD SP, n16
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state.SP = readPC16(); mcycles = 12; break;
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0x02: // LD [BC], A
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bus->write8(state.BC, state.A); mcycles = 8;;
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0x12: // LD [DE], A
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bus->write8(state.DE, state.A); mcycles = 8;;
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0x22: // LD [HL+], A
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bus->write8(state.HL, state.A); state.HL++; mcycles = 8;;
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0x32: // LD [HL-], A
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bus->write8(state.HL, state.A); state.HL--; mcycles = 8;;
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case 0x02: // LD [BC], A
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bus->write8(state.BC, state.A); mcycles = 8; break;
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case 0x12: // LD [DE], A
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bus->write8(state.DE, state.A); mcycles = 8; break;
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case 0x22: // LD [HL+], A
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bus->write8(state.HL, state.A); state.HL++; mcycles = 8; break;
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case 0x32: // LD [HL-], A
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bus->write8(state.HL, state.A); state.HL--; mcycles = 8; break;
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0x03: // INC BC
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state.BC++; mcycles = 2;;
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0x13: // INC DE
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state.DE++; mcycles = 2;;
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0x23: // INC HL
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state.HL++; mcycles = 2;;
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0x33: // INC SP
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state.SP++; mcycles = 2;;
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case 0x03: // INC BC
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state.BC++; mcycles = 2; break;
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case 0x13: // INC DE
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state.DE++; mcycles = 2; break;
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case 0x23: // INC HL
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state.HL++; mcycles = 2; break;
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case 0x33: // INC SP
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state.SP++; mcycles = 2; break;
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0x04: // INC B
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case 0x04: // INC B
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state.B++;
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state.zero = (state.B == 0);
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state.subtract = false;
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state.halfcarry = (state.B & 0x0F == 0);
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;
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0x14: // INC D
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break;
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case 0x14: // INC D
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state.D++;
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state.zero = (state.D == 0);
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state.subtract = false;
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state.halfcarry = (state.D & 0x0F == 0);
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;
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0x24: // INC H
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break;
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case 0x24: // INC H
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state.H++;
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state.zero = (state.H == 0);
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state.subtract = false;
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state.halfcarry = (state.H & 0x0F == 0);
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;
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0x34: // INC [HL]
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u8 data = bus->read8(state.HL);
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data++;
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bus->write8(state.HL, data);
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state.zero = (data == 0);
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state.subtract = false;
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state.halfcarry = (data & 0x0F == 0);
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break;
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case 0x34: // INC [HL]
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{
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u8 data = bus->read8(state.HL);
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data++;
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bus->write8(state.HL, data);
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state.zero = (data == 0);
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state.subtract = false;
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state.halfcarry = (data & 0x0F == 0);
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mcycles = 3;
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}
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break;
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case 0x05: // INC B
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state.B--;
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state.zero = (state.B == 0);
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state.subtract = true;
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state.halfcarry = (state.B & 0x0F == 0x0F);
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break;
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case 0x15: // INC D
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state.D--;
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state.zero = (state.D == 0);
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state.subtract = true;
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state.halfcarry = (state.D & 0x0F == 0x0F);
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break;
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case 0x25: // INC H
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state.H--;
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state.zero = (state.H == 0);
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state.subtract = true;
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state.halfcarry = (state.H & 0x0F == 0x0F);
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break;
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case 0x35: // INC [HL]
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{
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u8 data = bus->read8(state.HL);
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data--;
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bus->write8(state.HL, data);
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state.zero = (data == 0);
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state.subtract = true;
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state.halfcarry = (data & 0x0F == 0x0F);
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mcycles = 3;
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}
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break;
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case 0x06: // LD B, n8
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state.B = readPC8();
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mcycles = 2;
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break;
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case 0x16: // LD D, n8
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state.D = readPC8();
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mcycles = 2;
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break;
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case 0x26: // LD H, n8
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state.H = readPC8();
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mcycles = 2;
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break;
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case 0x36: // LD [HL], n8
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bus->write8(state.HL, readPC8());
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mcycles = 3;
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;
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break;
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}
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}
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@ -4,7 +4,7 @@ RAM::RAM(u16 size) : size(size), readonly(false) {
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memory = new u8[size];
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}
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RAM::RAM(u8* memory, u16 size, bool readonly = false)
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RAM::RAM(u8* memory, u16 size, bool readonly)
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: memory(memory), size(size), readonly(readonly)
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{}
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@ -25,7 +25,7 @@ void RAM::write16(u16 addr, u16 data) {
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}
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u16 RAM::read16(u16 addr) {
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if(addr >= size - 1) return;
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if(addr >= size - 1) return 0xFFFFu;
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u16 *ptr = (u16*)&memory[addr];
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return *ptr;
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}
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