WIP initial state

cpu/cpu.h

@@ -0,0 +1,62 @@
+#pragma once
+
+#include "types.h"
+
+class Cpu;
+class Mem_device;
+
+enum Flags {
+  F_ZERO = 0x8,
+  F_SUB = 0x4,
+  F_HALF = 0x2,
+  F_CARRY = 0x1,
+};
+
+union Register_pair {
+  struct { u8 hi; u8 lo; }
+  u16 hilo;
+};
+
+struct Cpu_state {
+  // Registers
+  union {
+    u16 BC;
+    struct { u8 B; u8 C; };
+  };
+  union {
+    u16 DE;
+    struct { u8 D; u8 E; };
+  };
+  union {
+    u16 HL;
+    struct { u8 H; u8 L; };
+  };
+
+  u8 A;
+  u16 SP;
+  u16 PC;
+
+  bool zero;
+  bool subtract;
+  bool halfcarry;
+  bool carry;
+};
+
+class Cpu {
+private:
+  Cpu_state state;
+  Mem_device* bus;
+
+  typedef u8 opcode_t;
+
+private:
+  u8 readPC();
+
+  void pushStack(u8 data);
+  u8 popStack();
+
+public:
+  Cpu();
+
+  void step();
+};

cpu/decoder.cpp

@@ -0,0 +1,108 @@
+#include "cpu/cpu.h"
+
+u8 Cpu::readPC8()
+{
+  u8 data = bus->read8(state.PC);
+  state.PC++;
+  return data;
+}
+
+u16 Cpu::readPC16()
+{
+  u16 data = bus->read16(state.PC);
+  state.PC+=2;
+  return data;
+}
+
+void pushStack8(u8 data)
+{
+  bus->write8(state.SP, data);
+  state.SP--;
+}
+
+u8 popStack8()
+{
+  u8 data = bus->read8(state.SP);
+  state.SP++;
+  return data;
+}
+
+void pushStack16(u16 data)
+{
+  bus->write16(state.SP,data);
+  state.SP-=2;
+}
+
+void popStack16()
+{
+  u16 data = bus->read16(state.SP);
+  state.SP+=2;
+  return data;
+}
+
+void Cpu::step()
+{
+  opcode_t op = readPC();
+  int mcycles = 1;
+  switch(op) {
+  0x00: // NOP
+    (void) ;;
+
+  0x01: // LD BC, n16
+    state.BC = readPC16(); mcycles = 12;;
+  0x11: // LD DE, n16
+    state.DE = readPC16(); mcycles = 12;;
+  0x21: // LD HL, n16
+    state.HL = readPC16(); mcycles = 12;;
+  0x31: // LD SP, n16
+    state.SP = readPC16(); mcycles = 12;;
+
+  0x02: // LD [BC], A
+    bus->write8(state.BC, state.A); mcycles = 8;;
+  0x12: // LD [DE], A
+    bus->write8(state.DE, state.A); mcycles = 8;;
+  0x22: // LD [HL+], A
+    bus->write8(state.HL, state.A); state.HL++; mcycles = 8;;
+  0x32: // LD [HL-], A
+    bus->write8(state.HL, state.A); state.HL--; mcycles = 8;;
+
+  0x03: // INC BC
+    state.BC++; mcycles = 2;;
+  0x13: // INC DE
+    state.DE++; mcycles = 2;;
+  0x23: // INC HL
+    state.HL++; mcycles = 2;;
+  0x33: // INC SP
+    state.SP++; mcycles = 2;;
+
+  0x04: // INC B
+    state.B++;
+    state.zero = (state.B == 0);
+    state.subtract = false;
+    state.halfcarry = (state.B & 0x0F == 0);
+    ;
+  0x14: // INC D
+    state.D++;
+    state.zero = (state.D == 0);
+    state.subtract = false;
+    state.halfcarry = (state.D & 0x0F == 0);
+    ;
+  0x24: // INC H
+    state.H++;
+    state.zero = (state.H == 0);
+    state.subtract = false;
+    state.halfcarry = (state.H & 0x0F == 0);
+    ;
+  0x34: // INC [HL]
+    u8 data = bus->read8(state.HL);
+    data++;
+    bus->write8(state.HL, data);
+    state.zero = (data == 0);
+    state.subtract = false;
+    state.halfcarry = (data & 0x0F == 0);
+    mcycles = 3;
+    ;
+
+
+  }
+}