WIP initial state
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10 changed files with 337 additions and 0 deletions
5
Makeconf
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5
Makeconf
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modules := test \
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memory/bus \
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memory/ram
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CXX_FLAGS := -I $(CURDIR)
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10
Makefile
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10
Makefile
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include Makeconf
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$(info $(modules))
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objs := $(addsuffix .o,$(modules))
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%.o: %.cpp
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g++ $(CXX_FLAGS) -c -o $@ $^
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vgbc: $(objs)
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g++ -o $@ $^
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62
cpu/cpu.h
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62
cpu/cpu.h
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#pragma once
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#include "types.h"
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class Cpu;
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class Mem_device;
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enum Flags {
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F_ZERO = 0x8,
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F_SUB = 0x4,
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F_HALF = 0x2,
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F_CARRY = 0x1,
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};
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union Register_pair {
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struct { u8 hi; u8 lo; }
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u16 hilo;
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};
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struct Cpu_state {
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// Registers
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union {
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u16 BC;
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struct { u8 B; u8 C; };
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};
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union {
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u16 DE;
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struct { u8 D; u8 E; };
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};
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union {
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u16 HL;
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struct { u8 H; u8 L; };
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};
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u8 A;
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u16 SP;
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u16 PC;
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bool zero;
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bool subtract;
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bool halfcarry;
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bool carry;
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};
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class Cpu {
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private:
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Cpu_state state;
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Mem_device* bus;
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typedef u8 opcode_t;
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private:
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u8 readPC();
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void pushStack(u8 data);
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u8 popStack();
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public:
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Cpu();
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void step();
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};
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108
cpu/decoder.cpp
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108
cpu/decoder.cpp
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#include "cpu/cpu.h"
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u8 Cpu::readPC8()
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{
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u8 data = bus->read8(state.PC);
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state.PC++;
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return data;
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}
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u16 Cpu::readPC16()
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{
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u16 data = bus->read16(state.PC);
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state.PC+=2;
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return data;
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}
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void pushStack8(u8 data)
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{
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bus->write8(state.SP, data);
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state.SP--;
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}
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u8 popStack8()
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{
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u8 data = bus->read8(state.SP);
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state.SP++;
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return data;
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}
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void pushStack16(u16 data)
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{
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bus->write16(state.SP,data);
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state.SP-=2;
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}
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void popStack16()
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{
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u16 data = bus->read16(state.SP);
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state.SP+=2;
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return data;
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}
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void Cpu::step()
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{
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opcode_t op = readPC();
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int mcycles = 1;
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switch(op) {
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0x00: // NOP
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(void) ;;
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0x01: // LD BC, n16
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state.BC = readPC16(); mcycles = 12;;
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0x11: // LD DE, n16
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state.DE = readPC16(); mcycles = 12;;
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0x21: // LD HL, n16
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state.HL = readPC16(); mcycles = 12;;
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0x31: // LD SP, n16
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state.SP = readPC16(); mcycles = 12;;
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0x02: // LD [BC], A
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bus->write8(state.BC, state.A); mcycles = 8;;
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0x12: // LD [DE], A
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bus->write8(state.DE, state.A); mcycles = 8;;
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0x22: // LD [HL+], A
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bus->write8(state.HL, state.A); state.HL++; mcycles = 8;;
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0x32: // LD [HL-], A
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bus->write8(state.HL, state.A); state.HL--; mcycles = 8;;
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0x03: // INC BC
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state.BC++; mcycles = 2;;
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0x13: // INC DE
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state.DE++; mcycles = 2;;
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0x23: // INC HL
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state.HL++; mcycles = 2;;
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0x33: // INC SP
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state.SP++; mcycles = 2;;
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0x04: // INC B
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state.B++;
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state.zero = (state.B == 0);
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state.subtract = false;
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state.halfcarry = (state.B & 0x0F == 0);
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;
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0x14: // INC D
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state.D++;
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state.zero = (state.D == 0);
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state.subtract = false;
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state.halfcarry = (state.D & 0x0F == 0);
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;
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0x24: // INC H
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state.H++;
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state.zero = (state.H == 0);
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state.subtract = false;
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state.halfcarry = (state.H & 0x0F == 0);
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;
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0x34: // INC [HL]
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u8 data = bus->read8(state.HL);
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data++;
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bus->write8(state.HL, data);
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state.zero = (data == 0);
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state.subtract = false;
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state.halfcarry = (data & 0x0F == 0);
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mcycles = 3;
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;
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}
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}
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51
memory/bus.cpp
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51
memory/bus.cpp
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#include "bus.h"
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Bus::Bus() : map() {}
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std::optional<Bus::MapEntry> Bus::find_entry(u16 addr)
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{
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for(auto it = map.begin(); it != map.end(); ++it)
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{
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if (addr >= it->start && addr <= it->end)
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return std::make_optional(*it);
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}
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return {};
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}
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void Bus::map_device(u16 start, u16 end, Mem_device* dev)
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{
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map.push_back(Bus::MapEntry{ start, end, dev });
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}
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void Bus::write8(u16 addr, u8 data)
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{
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auto mapentry = find_entry(addr);
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if(!mapentry) return;
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mapentry->dev->write8(addr - mapentry->start, data);
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}
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u8 Bus::read8(u16 addr)
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{
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auto mapentry = find_entry(addr);
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if(!mapentry) return 0xFFu;
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return mapentry->dev->read8(addr - mapentry->start);
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}
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void Bus::write16(u16 addr, u16 data)
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{
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auto mapentry = find_entry(addr);
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if(!mapentry) return;
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mapentry->dev->write16(addr - mapentry->start, data);
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}
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u16 Bus::read16(u16 addr)
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{
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auto mapentry = find_entry(addr);
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if(!mapentry) return 0xFFFFu;
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return mapentry->dev->read16(addr - mapentry->start);
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}
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31
memory/bus.h
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31
memory/bus.h
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#pragma once
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#include <vector>
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#include <optional>
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#include "mem_device.h"
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class Bus : public Mem_device {
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private:
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struct MapEntry {
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u16 start;
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u16 end;
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Mem_device *dev;
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};
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std::optional<MapEntry> find_entry(u16 addr);
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public:
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Bus();
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void map_device(u16 start, u16 end, Mem_device* dev);
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virtual void write8(u16 addr, u8 data);
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virtual u8 read8(u16 addr);
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virtual void write16(u16 addr, u16 data);
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virtual u16 read16(u16 addr);
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private:
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std::vector<MapEntry> map;
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};
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12
memory/mem_device.h
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12
memory/mem_device.h
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#pragma once
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#include "types.h"
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class Mem_device {
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public:
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virtual void write8(u16 addr, u8 data) = 0;
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virtual u8 read8(u16 addr) = 0;
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virtual void write16(u16 addr, u16 data) = 0;
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virtual u16 read16(u16 addr) = 0;
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};
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31
memory/ram.cpp
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31
memory/ram.cpp
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#include "ram.h"
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RAM::RAM(u16 size) : size(size), readonly(false) {
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memory = new u8[size];
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}
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RAM::RAM(u8* memory, u16 size, bool readonly = false)
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: memory(memory), size(size), readonly(readonly)
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{}
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void RAM::write8(u16 addr, u8 data) {
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if(addr >= size || readonly) return;
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memory[addr] = data;
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}
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u8 RAM::read8(u16 addr) {
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if (addr >= size) return 0xFFu;
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return memory[addr];
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}
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void RAM::write16(u16 addr, u16 data) {
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if(addr >= size - 1 || readonly) return;
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u16 *ptr = (u16*)&memory[addr];
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*ptr = data;
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}
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u16 RAM::read16(u16 addr) {
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if(addr >= size - 1) return;
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u16 *ptr = (u16*)&memory[addr];
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return *ptr;
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}
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20
memory/ram.h
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memory/ram.h
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#pragma once
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#include "mem_device.h"
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class RAM : public Mem_device {
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private:
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u8* memory;
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u16 size;
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bool readonly;
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public:
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RAM(u16 size);
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RAM(u8* memory, u16 size, bool readonly = false);
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virtual void write8(u16 addr, u8 data);
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virtual u8 read8(u16 addr);
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virtual void write16(u16 addr, u16 data);
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virtual u16 read16(u16 addr);
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};
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7
types.h
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7
types.h
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#pragma once
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typedef unsigned char u8;
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typedef unsigned short u16;
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typedef signed char s8;
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typedef signed short s16;
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