Commit graph

55 commits

Author SHA1 Message Date
175a24c77d cpu/decoder - define opcode class with methods
Instead of doing the same bit operations on the opcode everywhere, and
possibly botching it in the process, we create a datatype which has
methods return often used values extracted from the opcode.
2023-08-30 18:27:53 +02:00
ef9bda4a30 cpu/decoder - Little conversion fix for ADD SP, e8 2023-08-30 13:43:10 +02:00
53daaeba6b cpu/decoder - Remove more extraneous brackets 2023-08-30 13:41:35 +02:00
a8edf40b96 cpu/decoder - Unify code for ALU n ops 2023-08-30 13:41:15 +02:00
9bc6f935ac cpu/decoder - Fix comment 2023-08-30 13:40:50 +02:00
77bd32114a cpu/decoder - Join code for INC rr and DEC rr 2023-08-30 13:34:14 +02:00
e45704e2ab cpu/decoder - Reduct empty lines 2023-08-30 13:27:04 +02:00
dbd42c4573 cpu/decoder - Remove extraneous brackets 2023-08-30 13:26:35 +02:00
87b939c80e cpu/decoder - add function with shared code for 16-bit addition 2023-08-30 13:20:57 +02:00
3d244d1ec0 cpu/decoder - Implement DAA
This is a best effort implementation, possible quirks of the actual
hardware have not been considered.
2023-08-30 12:56:00 +02:00
2d4daf821e cpu/decoder - Add missing breaks 2023-08-30 12:32:38 +02:00
7d1d20becf cpu/decoder - Fix comment 2023-08-30 00:36:20 +02:00
efc6762068 cpu/decoder - Remove extaneous code of instruction already implemented elsewhere 2023-08-30 00:25:49 +02:00
aec3c7b0e6 cpu - Fix build errors 2023-08-30 00:01:45 +02:00
c4a9a10e09 cpu/decoder - Treat undefined opcodes as NOP 2023-08-29 23:59:32 +02:00
c90788d330 cpu/decoder - Implement STOP n8 2023-08-29 23:47:18 +02:00
2ab37c6468 cpu/cpu - Implement stop mode 2023-08-29 23:46:36 +02:00
4e506a4d3c cpu/decoder - Implement LD HL, SP + e8 2023-08-29 23:46:09 +02:00
7180ae8c40 cpu/decoder - Implement HALT 2023-08-29 23:32:11 +02:00
5cabe03d25 cpu/cpu - Handle halt mode 2023-08-29 23:30:31 +02:00
5281ceb0d6 cpu/cpu - Fix include 2023-08-29 23:16:18 +02:00
7425663f16 Move types.h to misc 2023-08-29 23:16:09 +02:00
eb0e591b25 Move panic.h to misc 2023-08-29 23:15:00 +02:00
ef2615c1a7 cpu/decoder - Fix build errors 2023-08-29 23:13:23 +02:00
517577d546 Improve consistency for including 2023-08-29 23:11:31 +02:00
c39a680293 cpu/decoder - Fix IME state for RETI 2023-08-29 23:06:50 +02:00
28bc389644 cpu/decoder - Reset carry flag for PREFIX SWAP instruction 2023-08-29 23:06:28 +02:00
b6f0f4416f cpu/decoder - Implement ADD SP, e8 2023-08-29 23:06:05 +02:00
41c4038d0a cpu/decoder - Implement ADD HL, rr 2023-08-29 23:05:55 +02:00
8f1b1eb924 cpu/decoder - Implement INC rr and DEC rr 2023-08-29 23:04:59 +02:00
e893d2b9f5 cpu/decoder - Use variable instead calculating twice 2023-08-29 23:04:31 +02:00
43088a7f99 cpu/decoder - Remove extraneous comments 2023-08-29 21:27:32 +02:00
39e041f473 cpu/decoder - Implement RLCA, RLA, RRCA, RRA 2023-08-29 21:25:19 +02:00
7902ac4641 cpu/decoder - little code improvement 2023-08-29 21:14:19 +02:00
50cac936b9 cpu/decoder - Implement PREFIX (bit shift & bit ops) 2023-08-29 21:00:37 +02:00
8160037ffc cpu/decoder - Improve code formatting 2023-08-29 19:43:19 +02:00
40b5d1d370 cpu/decoder - Fix decoding of JR e instruction 2023-08-29 19:42:42 +02:00
8383256d7e cpu - Fix order of 8-bit registers in memory 2023-08-29 19:42:01 +02:00
ddea64ec63 cpu/decoder - Remove unnessary intermediate variable 2023-08-29 16:54:17 +02:00
c08fd5d68d cpu/decoder - Actually use pushStack16 and popStack16 for POP and PUSH 2023-08-29 16:53:53 +02:00
310fb99ad2 cpu/decoder - Simplify decoding by referencing registers by index 2023-08-29 16:53:20 +02:00
eabc39590e cpu/panic - Improve declaration 2023-08-29 16:51:58 +02:00
216cf660a1 cpu/cpu - Add way to signal interrupt from outside 2023-08-29 13:45:55 +02:00
7aa1af40fb cpu/cpu - Treat a call to an ISR as a step 2023-08-29 13:45:46 +02:00
1fc081b3c5 cpu - Fix push operations 2023-08-29 12:10:10 +02:00
002b745917 cpu - Fix timing of delay when enabling interrupts 2023-08-29 12:10:10 +02:00
763fe13f5a decoder - Disable debug printf 2023-08-28 23:08:33 +02:00
bd2b577c6c decoder - Add parenthesis to bitwise ANDs
== has priority over & so a & b == c is parsed as a & (b == c)
2023-08-28 22:31:52 +02:00
505478b840 Improve Cpu class and implement interrupts 2023-08-28 21:56:33 +02:00
e4a6b1f9b4 decoder - Simplify RST command
We can calculate the rst address directly from the op code.
2023-08-28 19:39:18 +02:00