#include #include LCD::LCD(Cpu& cpu) : screenbuffer(), regLY(0), regLYC(0), intHBlank(false), intVBlank(false), intOAM(false), intLYC(false), cpu(cpu), bgp(false), obp{Palette(true),Palette(true)}, vram_dirty(true) { screenbuffer.create(160,144); screenbuffer.clear(); std::memset(vram_raw, 0, 0x2000); for(int i = 0; i < 256; i++) tilemap[i].create(8,8); } void LCD::write8(u16 addr, u8 data) { // VRAM access if (Range(0x8000,0x9FFF).contains(addr)) { vram_raw[addr-0x8000] = data; vram_dirty = true; return; } switch(addr) { case 0xFF40: // LCDC // TODO break; case 0xFF41: // STAT intHBlank = data & IntSourceHBlank; intVBlank = data & IntSourceVBlank; intOAM = data & IntSourceOAM; intLYC = data & IntSourceLYC; break; case 0xFF42: // SCY // TODO break; case 0xFF43: // SCX // TODO break; case 0xFF44: // LY // Ignore break; case 0xFF45: // LYC regLYC = data; break; case 0xFF46: // DMA (OAM DMA source address) // TODO break; case 0xFF47: // BGP bgp.setRegValue(data); vram_dirty = true; break; case 0xFF48: // OBP0 obp[0].setRegValue(data); vram_dirty = true; break; case 0xFF49: // OBP1 obp[1].setRegValue(data); vram_dirty = true; break; case 0xFF4A: // WY case 0xFF4B: // WX // TODO break; } } u8 LCD::read8(u16 addr) { // VRAM access if (Range(0x8000,0x9FFF).contains(addr)) return vram_raw[addr-0x8000]; switch(addr) { case 0xFF40: // LCDC // TODO return 0x00; case 0xFF41: // STAT return (currentMode | (regLY == regLYC ? LycEqual : 0) | (intHBlank ? IntSourceHBlank : 0) | (intVBlank ? IntSourceVBlank : 0) | (intOAM ? IntSourceOAM : 0) | (intLYC ? IntSourceLYC : 0)); case 0xFF42: // SCY // TODO return 0x00; case 0xFF43: // SCX // TODO return 0x00; case 0xFF44: // LY return regLY; case 0xFF45: // LYC return regLYC; case 0xFF46: // DMA (OAM DMA source address) // TODO return 0x00; case 0xFF47: // BGP return bgp.getRegValue(); case 0xFF48: // OBP0 return obp[0].getRegValue(); case 0xFF49: // OBP1 return obp[1].getRegValue(); case 0xFF4A: // WY case 0xFF4B: // WY // TODO return 0x00; default: return 0xFF; } }