476 lines
12 KiB
C++
476 lines
12 KiB
C++
#include "cpu/cpu.h"
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#include "cpu/panic.h"
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#include "memory/mem_device.h"
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static inline u16 make_u16(u8 msb, u8 lsb)
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{
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return (((u16)msb << 8) | (u16)lsb);
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}
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void Cpu::executeInstruction()
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{
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u16 currentpc = state.PC;
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opcode_t op = readPC8();
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int mcycles = 1;
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#if 0
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printf("@0x%04x: opcode %02X\n",currentpc,op);
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#endif
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if ((op & 0xC0) == 0x40 && op != 0x76) // LD r, r'
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{
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u8 tmp;
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switch(op & 0x07)
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{
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case 0x6: tmp = bus->read8(state.HL); break;
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default: tmp = state.reg8(op & 0x07); break;
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};
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switch((op >> 3) & 0x7)
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{
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case 0x6: bus->write8(state.HL, tmp); break;
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default: state.reg8((op >> 3) & 0x7) = tmp; break;
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}
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}
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else if((op & 0xC7) == 0x06) // LD r, n
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{
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u8 imm = readPC8();
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switch((op >> 3) & 0x7)
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{
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case 0x6: bus->write8(state.HL, imm); break;
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default: state.reg8((op >> 3) & 0x7) = imm; break;
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}
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}
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else if((op & 0xC7) == 0x46 && op != 0x76) // LD r, [HL]
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{
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u8 data = bus->read8(state.HL);
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state.reg8((op >> 3) & 0x7) = data;
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}
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else if((op & 0xC8) == 0x70 && op != 0x76) // LD [HL], r
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{
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u8 data = state.reg8(op & 0x7);
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bus->write8(state.HL, data);
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}
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else if((op & 0xCF) == 0x01) // LD rr, nn
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{
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u16 data = readPC16();
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state.reg16((op >> 4) & 0x3) = data;
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mcycles = 3;
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}
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else if((op & 0xCF) == 0xC5) // PUSH rr
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{
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u16 data;
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switch((op >> 4) & 0x3)
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{
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case 0x3: data = state.getAF(); break;
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default: data = state.reg16((op >> 4) & 0x3);
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}
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pushStack16(data);
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mcycles = 4;
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}
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else if((op & 0xCF) == 0xC1) // POP rr
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{
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u16 data = popStack16();
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switch((op >> 4) & 0x3)
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{
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case 0x3: state.setAF(data); break;
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default: state.reg16((op >> 4) & 0x3) = data; break;
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}
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mcycles = 4;
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}
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else if((op & 0xC0) == 0x80) // ADD, ADC, SUB, ABC, CP, AND, OR, XOR
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{
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AluOp aluop = (AluOp)((op >> 3) & 0x3);
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u8 reg = op & 0x7;
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u8 rhs;
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switch(reg)
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{
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case 0x6: rhs = bus->read8(state.HL); mcycles = 2; break;
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default: rhs = state.reg8(reg); break;
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}
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aluop8(aluop, rhs);
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}
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else if((op & 0xC6) == 0x04) // INC r; INC [HL]; DEC r; DEC [HL];
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{
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AluOp aluop = (op & 0x1) ? SUB : ADD;
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switch((op >> 3) & 0x7)
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{
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case 0x6:
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{
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u8 tmp = bus->read8(state.HL);
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aluop8(aluop, tmp, 1, tmp, false);
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bus->write8(state.HL, tmp);
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mcycles = 3;
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}
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break;
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default:
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{
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u8& reg = state.reg8((op >> 3) & 0x7);
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aluop8(aluop, reg, 1, reg, false); break;
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}
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break;
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}
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}
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else if((op & 0xCF) == 0x03) // INC rr
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{
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state.reg16((op >> 4) & 0x3) += 1;
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mcycles = 2;
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}
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else if((op & 0xCF) == 0x0B) // INC rr
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{
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state.reg16((op >> 4) & 0x3) -= 1;
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mcycles = 2;
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}
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else if((op & 0xE7) == 0xC2) // JP cc, nn:
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{
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u16 nn = readPC16();
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if (decodeCond((op >> 3) && 0x3))
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{
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state.PC = nn;
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mcycles = 4;
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}
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else
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{
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mcycles = 3;
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}
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}
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else if((op & 0xE7) == 0x20) // JR cc, e
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{
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s8 e = readPC8();
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bool cond;
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if (decodeCond((op >> 3) & 0x3))
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{
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state.PC += e;
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mcycles = 3;
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}
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else
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{
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mcycles = 2;
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}
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}
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else if((op & 0xE7) == 0xC4) // CALL cc, nn
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{
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u16 nn = readPC16();
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if(decodeCond((op >> 3) & 0x3))
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{
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doCall(nn);
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mcycles = 6;
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}
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else
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{
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mcycles = 3;
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}
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}
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else if((op & 0xCF) == 0x09) // ADD HL, rr
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{
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u16 rhs = state.reg16((op >> 4) & 0x3);
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u16 res12 = (state.HL & 0x0FFF) + (rhs & 0x0FFF);
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state.halfcarry = (res11 & 0x1000);
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u32 res32 = (u32)state.HL + (u32)rhs;
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state.carry = (res32 & 0x10000);
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state.subtract = false;
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mcycles = 2;
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}
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else if((op & 0xE7) == 0xC0) // RET cc
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{
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if(decodeCond((op >> 3) & 0x3))
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{
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doRet();
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mcycles = 5;
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}
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else
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{
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mcycles = 2;
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}
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}
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else if((op & 0xC7) == 0xC7) // RST
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{
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u16 rst_addr = op & 0x38;
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doCall(rst_addr);
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}
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else if(op == 0xCB) // PREFIX
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{
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currentpc = state.PC;
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opcode_t prefix_op = readPC8();
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#if 0
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printf("@0x%04x: CB opcode %02X\n", currentpc, prefix_op);
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#endif
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u8 reg = prefix_op & 0x7;
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u8 data;
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switch(reg)
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{
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case 0x6: data = bus->read8(state.HL); mcycles = 3; break;
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default: data = state.reg8(reg); mcycles = 2; break;
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}
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// For BIT, RES, SET
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u8 bit = (prefix_op >> 3) & 0x7;
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switch(prefix_op & 0xC0)
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{
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case 0x00:
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switch(prefix_op & 0xF1)
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{
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case 0x00: // RLC
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{
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bool msb_set = (data & 0x80);
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data = (data << 1) | (msb_set ? 0x1 : 0x0);
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state.carry = msb_set;
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}
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break;
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case 0x08: // RRC
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{
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bool lsb_set = (data & 0x01);
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data = (data >> 1) | (lsb_set ? 0x80 : 0x00);
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state.carry = lsb_set;
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}
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break;
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case 0x10: // RL
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{
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bool msb_set = (data & 0x80);
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data = (data << 1) | (state.carry ? 0x1 : 0x0);
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state.carry = msb_set;
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}
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break;
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case 0x18: // RR
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{
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bool lsb_set = (data & 0x01) != 0;
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data = (data >> 1) | (state.carry ? 0x80 : 0x00);
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state.carry = lsb_set;
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}
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break;
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case 0x20: // SLA
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state.carry = (data & 0x80);
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data = (data << 1);
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break;
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case 0x28: // SRA
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state.carry = (data & 0x01);
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data = (data >> 1) | (data & 0x80);
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break;
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case 0x30: // SWAP
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data = ((data >> 4) & 0x0F) | ((data << 4) & 0xF0);
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break;
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case 0x38: // SRL
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state.carry = (data & 0x01);
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data = (data >> 1);
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break;
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}
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state.halfcarry = false;
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state.subtract = false;
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state.zero = (data == 0);
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break;
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case 0x40: // BIT
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state.zero = (data & (1 << bit)) == 0;
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state.subtract = false;
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state.halfcarry = true;
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break;
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case 0x80: // RES
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data &= ~(1 << bit);
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break;
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case 0xC0: // SET
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data |= (1 << bit);
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break;
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}
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// All ops except for BIT write the data back to where it came from
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if ((prefix_op & 0xC0) != 0x40)
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{
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switch(reg)
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{
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case 0x6: bus->write8(state.HL, data); mcycles = 4; break;
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default: state.reg8(reg) = data; break;
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}
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}
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}
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else
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{
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switch(op)
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{
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case 0x00: break; // NOP
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case 0x0A: // Load A, [BC]
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state.A = bus->read8(state.BC);
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mcycles = 2;
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break;
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case 0x1A: // Load A, [DE]
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state.A = bus->read8(state.DE);
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mcycles = 2;
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break;
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case 0x02: // Load [BC], A
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bus->write8(state.BC, state.A);
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mcycles = 2;
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break;
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case 0x12: // Load [DE], A
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bus->write8(state.DE, state.A);
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mcycles = 2;
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break;
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case 0x07: // RLCA
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{
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state.carry = (state.A & 0x80);
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state.A = (state.A << 1) | (state.carry ? 0x01 : 0x00);
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state.halfcarry = false;
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state.subtract = false;
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state.zero = false;
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}
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case 0x17: // RLA
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{
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bool msb_set = (state.A & 0x80);
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state.A = (state.A << 1) | (state.carry ? 0x01 : 0x00);
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state.carry = msb_set;
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state.halfcarry = false;
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state.subtract = false;
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state.zero = false;
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}
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case 0x0F: // RRCA
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{
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state.carry = (state.A & 0x01);
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state.A = (state.A >> 1) | (state.carry ? 0x80 : 0x00);
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state.halfcarry = false;
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state.subtract = false;
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state.zero = false;
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}
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case 0x1F: // RRA
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{
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bool lsb_set = (state.A & 0x01);
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state.A = (state.A >> 1) | (state.carry ? 0x80 : 0x00);
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state.carry = lsb_set;
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state.halfcarry = false;
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state.subtract = false;
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state.zero = false;
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}
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case 0xFA: // LD A, [nn]
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state.A = bus->read8(readPC16());
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mcycles = 4;
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break;
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case 0xEA: // LD [nn], A
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bus->write8(readPC16(), state.A);
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mcycles = 4;
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break;
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case 0xF2: // LD A, [0xFF : C]
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state.A = bus->read8(make_u16(0xFFu,state.C));
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mcycles = 2;
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break;
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case 0xE2: // LD [0xFF : C], A
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bus->write8(make_u16(0xFFu,state.C), state.A);
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mcycles = 2;
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break;
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case 0xF0: // LD A, [0xFF : n]
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state.A = bus->read8(make_u16(0xFFu,readPC8()));
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mcycles = 3;
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break;
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case 0xE0: // LD [0xFF : n], A
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bus->write8(make_u16(0xFFu,readPC8()), state.A);
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mcycles = 3;
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break;
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case 0x3A: // LD A, [HL-]
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state.A = bus->read8(state.HL); state.HL--; mcycles = 2; break;
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case 0x2A: // LD A, [HL+]
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state.A = bus->read8(state.HL); state.HL++; mcycles = 2; break;
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case 0x32: // LD [HL-], A
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bus->write8(state.HL, state.A); state.HL--; mcycles = 2; break;
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case 0x22: // LD [HL-], A
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bus->write8(state.HL, state.A); state.HL++; mcycles = 2; break;
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case 0x08: // LD [nn], SP
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bus->write16(readPC16(), state.SP); mcycles = 5; break;
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case 0xF9: // LD SP, HL
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state.SP = state.HL; mcycles = 2; break;
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case 0xC6: // ADD n
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aluop8(ADD, readPC8()); mcycles = 2; break;
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case 0xD6: // SUB n
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aluop8(SUB, readPC8()); mcycles = 2; break;
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case 0xE6: // AND n
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aluop8(AND, readPC8()); mcycles = 2; break;
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case 0xF6: // OR n
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aluop8(OR, readPC8()); mcycles = 2; break;
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case 0xCE: // ADC n
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aluop8(ADC, readPC8()); mcycles = 2; break;
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case 0xDE: // SBC n
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aluop8(SBC, readPC8()); mcycles = 2; break;
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case 0xEE: // XOR n
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aluop8(XOR, readPC8()); mcycles = 2; break;
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case 0xFE: // CP n
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aluop8(CP, readPC8()); mcycles = 2; break;
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case 0x3F: // CCF complement carry flag
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state.carry = !state.carry;
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state.subtract = false;
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state.halfcarry = false;
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break;
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case 0x37: // SCF Set carry flag
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state.carry = true;
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state.subtract = false;
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state.halfcarry = false;
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break;
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// TODO: case 0x27: break; // DAA
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case 0x2F: // CPL Complement accumulator
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state.A = ~state.A;
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state.subtract = true;
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state.halfcarry = true;
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case 0xC3: // JP nn
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state.PC = readPC16();
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mcycles = 4;
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break;
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case 0xE9: // JP HL
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state.PC = state.HL;
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break;
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case 0x18: // JR e
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state.PC += (s8)readPC8();
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break;
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case 0xCD: // CALL nn
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doCall(readPC16());
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mcycles = 6;
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break;
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case 0xC9: // RET
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doRet();
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mcycles = 4;
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break;
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case 0xD9: // RETI
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doRet();
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state.IME = IME_ON;
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mcycles = 4;
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break;
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case 0xF3: // DI
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state.IME = IME_OFF;
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break;
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case 0xFB: // EI
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state.IME = IME_SCHEDULED;
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break;
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case 0xE8: // ADD SP, e8
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u32 lhs = state.SP;
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s32 rhs = (s8)readPC8();
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u32 low_add = (lhs & 0x0FFF) + (rhs & 0x0FFF);
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state.halfcarry = (low_add & 0x1000);
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u32 res32 = lhs + rhs;
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state.carry = (res32 & 0x10000);
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state.SP = (u16)res32;
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state.subtract = false;
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state.zero = false;
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mcycles = 4;
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default:
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panic("Unknown opcode 0x%x\n",op);
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}
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}
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processed_mcycles += mcycles;
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}
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