2023-08-26 19:04:02 +02:00
|
|
|
#pragma once
|
|
|
|
|
|
|
|
#include "types.h"
|
|
|
|
|
2023-08-28 21:56:33 +02:00
|
|
|
#include "memory/mem_device.h"
|
|
|
|
|
|
|
|
typedef u8 opcode_t;
|
2023-08-26 19:04:02 +02:00
|
|
|
|
|
|
|
enum Flags {
|
|
|
|
F_ZERO = 0x8,
|
|
|
|
F_SUB = 0x4,
|
|
|
|
F_HALF = 0x2,
|
|
|
|
F_CARRY = 0x1,
|
|
|
|
};
|
|
|
|
|
2023-08-27 22:19:02 +02:00
|
|
|
enum AluOp : int {
|
|
|
|
ADD = 0,
|
|
|
|
ADC = 1,
|
|
|
|
SUB = 2,
|
|
|
|
SBC = 3,
|
|
|
|
AND = 4,
|
|
|
|
XOR = 5,
|
|
|
|
OR = 6,
|
|
|
|
CP = 7,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum CC
|
|
|
|
{
|
|
|
|
COND_NZ = 0,
|
|
|
|
COND_Z = 1,
|
|
|
|
COND_NC = 2,
|
|
|
|
COND_C = 3,
|
|
|
|
};
|
|
|
|
|
2023-08-28 21:56:33 +02:00
|
|
|
enum InterruptType : u8
|
|
|
|
{
|
|
|
|
INT_VBlank = 0x1,
|
|
|
|
INT_LCDSTAT = 0x2,
|
|
|
|
INT_Timer = 0x4,
|
|
|
|
INT_Serial = 0x8,
|
|
|
|
INT_Joypad = 0x10,
|
|
|
|
|
|
|
|
INT_MASK = 0x1F,
|
|
|
|
};
|
|
|
|
|
2023-08-29 12:10:10 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
IME - Interrupt Master Enable
|
|
|
|
|
|
|
|
An EI instruction will enable the interrupts, but delayed. During the next instruction after EI,
|
|
|
|
interrupts are still disabled. For this to be emulated we use a small state machine. which works as follows
|
|
|
|
|
|
|
|
instruction EI - sets IME_SCHEDULED
|
|
|
|
handleInterrupts -> IME_SCHEDULED to IME_ON (but no call to isr yet)
|
|
|
|
instruction any - is IME_ON, but no chance for call to isr yet
|
|
|
|
handleInterrupts -> is IME_ON, do a call to isr if necessary
|
|
|
|
*/
|
2023-08-28 21:56:33 +02:00
|
|
|
enum IME_state
|
|
|
|
{
|
|
|
|
IME_OFF,
|
|
|
|
IME_SCHEDULED,
|
|
|
|
IME_ON,
|
|
|
|
};
|
2023-08-27 22:19:02 +02:00
|
|
|
|
2023-08-26 19:04:02 +02:00
|
|
|
struct Cpu_state {
|
|
|
|
// Registers
|
|
|
|
union {
|
|
|
|
u16 BC;
|
|
|
|
struct { u8 B; u8 C; };
|
|
|
|
};
|
|
|
|
union {
|
|
|
|
u16 DE;
|
|
|
|
struct { u8 D; u8 E; };
|
|
|
|
};
|
|
|
|
union {
|
|
|
|
u16 HL;
|
|
|
|
struct { u8 H; u8 L; };
|
|
|
|
};
|
|
|
|
|
|
|
|
u8 A;
|
|
|
|
u16 SP;
|
|
|
|
u16 PC;
|
|
|
|
|
|
|
|
bool zero;
|
|
|
|
bool subtract;
|
|
|
|
bool halfcarry;
|
|
|
|
bool carry;
|
2023-08-27 22:19:02 +02:00
|
|
|
|
2023-08-28 21:56:33 +02:00
|
|
|
IME_state IME;
|
2023-08-27 22:19:02 +02:00
|
|
|
|
2023-08-28 21:56:33 +02:00
|
|
|
u8 IE;
|
|
|
|
u8 IF;
|
2023-08-27 22:19:02 +02:00
|
|
|
|
|
|
|
void setAF(u16 v);
|
|
|
|
u16 getAF();
|
2023-08-26 19:04:02 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
class Cpu {
|
|
|
|
private:
|
2023-08-26 21:17:47 +02:00
|
|
|
u8 readPC8();
|
|
|
|
u16 readPC16();
|
2023-08-26 19:04:02 +02:00
|
|
|
|
2023-08-26 21:17:47 +02:00
|
|
|
void pushStack8(u8 data);
|
|
|
|
u8 popStack8();
|
2023-08-26 19:04:02 +02:00
|
|
|
|
2023-08-26 21:17:47 +02:00
|
|
|
void pushStack16(u16 data);
|
|
|
|
u16 popStack16();
|
2023-08-27 22:19:02 +02:00
|
|
|
|
|
|
|
void aluop8(AluOp op, u8 lhs, u8 rhs, u8& out, bool update_carry = true);
|
|
|
|
|
|
|
|
inline
|
|
|
|
void aluop8(AluOp op, u8 rhs, bool update_carry = true)
|
|
|
|
{
|
|
|
|
aluop8(op, state.A, rhs, state.A, update_carry);
|
|
|
|
}
|
|
|
|
|
|
|
|
void doCall(u16 target);
|
|
|
|
void doRet();
|
|
|
|
|
|
|
|
bool decodeCond(u8 cc);
|
|
|
|
|
2023-08-28 21:56:33 +02:00
|
|
|
void handleInterrupts();
|
|
|
|
void executeInstruction();
|
|
|
|
|
|
|
|
void reset();
|
|
|
|
|
2023-08-26 19:04:02 +02:00
|
|
|
public:
|
2023-08-28 21:56:33 +02:00
|
|
|
Cpu(Mem_device* bus);
|
|
|
|
|
|
|
|
Cpu_state state;
|
|
|
|
Mem_device* bus;
|
|
|
|
unsigned long processed_mcycles;
|
|
|
|
|
|
|
|
|
|
|
|
void signal(InterruptType it);
|
|
|
|
void setIE(u8 val);
|
|
|
|
u8 getIE();
|
2023-08-26 19:04:02 +02:00
|
|
|
|
|
|
|
void step();
|
|
|
|
};
|