vgbc/cpu/decoder.cpp

#include "cpu/cpu.h"
#include "memory/mem_device.h"

u8 Cpu::readPC8()
{
  u8 data = bus->read8(state.PC);
  state.PC++;
  return data;
}

u16 Cpu::readPC16()
{
  u16 data = bus->read16(state.PC);
  state.PC+=2;
  return data;
}

void Cpu::pushStack8(u8 data)
{
  bus->write8(state.SP, data);
  state.SP--;
}

u8 Cpu::popStack8()
{
  u8 data = bus->read8(state.SP);
  state.SP++;
  return data;
}

void Cpu::pushStack16(u16 data)
{
  bus->write16(state.SP,data);
  state.SP-=2;
}

u16 Cpu::popStack16()
{
  u16 data = bus->read16(state.SP);
  state.SP+=2;
  return data;
}

void Cpu::step()
{
  opcode_t op = readPC8();
  int mcycles = 1;

  switch(op) {
  case 0x00: break; // NOP

  case 0x01: // LD BC, n16
    state.BC = readPC16(); mcycles = 12; break;
  case 0x11: // LD DE, n16
    state.DE = readPC16(); mcycles = 12; break;
  case 0x21: // LD HL, n16
    state.HL = readPC16(); mcycles = 12; break;
  case 0x31: // LD SP, n16
    state.SP = readPC16(); mcycles = 12; break;

  case 0x02: // LD [BC], A
    bus->write8(state.BC, state.A); mcycles = 8; break;
  case 0x12: // LD [DE], A
    bus->write8(state.DE, state.A); mcycles = 8; break;
  case 0x22: // LD [HL+], A
    bus->write8(state.HL, state.A); state.HL++; mcycles = 8; break;
  case 0x32: // LD [HL-], A
    bus->write8(state.HL, state.A); state.HL--; mcycles = 8; break;

  case 0x03: // INC BC
    state.BC++; mcycles = 2; break;
  case 0x13: // INC DE
    state.DE++; mcycles = 2; break;
  case 0x23: // INC HL
    state.HL++; mcycles = 2; break;
  case 0x33: // INC SP
    state.SP++; mcycles = 2; break;

  case 0x04: // INC B
    state.B++;
    state.zero = (state.B == 0);
    state.subtract = false;
    state.halfcarry = (state.B & 0x0F == 0);
    break;
  case 0x14: // INC D
    state.D++;
    state.zero = (state.D == 0);
    state.subtract = false;
    state.halfcarry = (state.D & 0x0F == 0);
    break;
  case 0x24: // INC H
    state.H++;
    state.zero = (state.H == 0);
    state.subtract = false;
    state.halfcarry = (state.H & 0x0F == 0);
    break;
  case 0x34: // INC [HL]
    {
      u8 data = bus->read8(state.HL);
      data++;
      bus->write8(state.HL, data);
      state.zero = (data == 0);
      state.subtract = false;
      state.halfcarry = (data & 0x0F == 0);
      mcycles = 3;
    }
    break;

  case 0x05: // INC B
    state.B--;
    state.zero = (state.B == 0);
    state.subtract = true;
    state.halfcarry = (state.B & 0x0F == 0x0F);
    break;
  case 0x15: // INC D
    state.D--;
    state.zero = (state.D == 0);
    state.subtract = true;
    state.halfcarry = (state.D & 0x0F == 0x0F);
    break;
  case 0x25: // INC H
    state.H--;
    state.zero = (state.H == 0);
    state.subtract = true;
    state.halfcarry = (state.H & 0x0F == 0x0F);
    break;
  case 0x35: // INC [HL]
    {
      u8 data = bus->read8(state.HL);
      data--;
      bus->write8(state.HL, data);
      state.zero = (data == 0);
      state.subtract = true;
      state.halfcarry = (data & 0x0F == 0x0F);
      mcycles = 3;
    }
    break;

  case 0x06: // LD B, n8
    state.B = readPC8();
    mcycles = 2;
    break;
  case 0x16: // LD D, n8
    state.D = readPC8();
    mcycles = 2;
    break;
  case 0x26: // LD H, n8
    state.H = readPC8();
    mcycles = 2;
    break;
  case 0x36: // LD [HL], n8
    bus->write8(state.HL, readPC8());
    mcycles = 3;
    break;
  }
}