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more decoder code

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madmaurice 2023-08-26 23:51:51 +02:00
parent 8d063c08ca
commit ab09bbd9b7
1 changed files with 295 additions and 103 deletions
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194
cpu/decoder.cpp
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@ -46,7 +46,41 @@ void Cpu::step()
opcode_t op = readPC8();
int mcycles = 1;
switch(op) {
if ((op & 0xC0 == 0x40) && op != 0x76) // Lots of LD (0x76 is HALT)
{
u9 tmp;
switch(op & 0x07)
{
case 0x0: tmp = state.B; break;
case 0x1: tmp = state.C; break;
case 0x2: tmp = state.D; break;
case 0x3: tmp = state.E; break;
case 0x4: tmp = state.H; break;
case 0x5: tmp = state.L; break;
case 0x6: tmp = bus->read8(state.HL); break;
case 0x7: tmp = state.A; break;
};
switch(op & 0x38)
{
case 0x00: state.B = tmp; break;
case 0x10: state.D = tmp; break;
case 0x20: state.H = tmp; break;
case 0x30: bus->write8(state.HL, tmp); break;
case 0x08: state.C = tmp; break;
case 0x18: state.E = tmp; break;
case 0x28: state.L = tmp; break;
case 0x38: state.A = tmp; break;
}
}
else if(op & 0xC7 == 0x06)
{
}
else
{
switch(op)
{
case 0x00: break; // NOP
case 0x01: // LD BC, n16
@ -152,5 +186,163 @@ void Cpu::step()
bus->write8(state.HL, readPC8());
mcycles = 3;
break;
case 0x07: // RLCA
case 0x17: // RLA
case 0x27: // DAA
case 0x37: // SCF
break;
case 0x08: // LD [a16], SP
{
u16 addr = readPC16();
bus->write16(addr, state.SP);
mcycles = 5;
}
break;
case 0x18: // JR e8
{
s8 rel = readPC8();
state.PC = state.PC + rel;
mcycles = 3;
}
break;
case 0x28: // JR Z, e8
{
s8 rel = readPC8();
if (state.zero)
{
state.PC = state.PC + rel;
mcycles = 3;
}
else
{
mcycles = 2;
}
}
break;
case 0x38: // JR C, e8
{
s8 rel = readPC8();
if (state.carry)
{
state.PC = state.PC + rel;
mcycles = 3;
}
else
{
mcycles = 2;
}
}
break;
case 0x09: // ADD HL, BC
case 0x19: // ADD HL, DE
case 0x29: // ADD HL, HL
case 0x39: // ADD HL, SP
// TODO
break;
case 0x0A: // LD A, [BC]
state.A = bus->read8(state.BC);
break;
case 0x1A: // LD A, [DE]
state.A = bus->read8(state.DE);
break;
case 0x2A: // LD A, [HL+]
state.A = bus->read8(state.HL);
state.HL++;
break;
case 0x3A: // LD A, [HL-]
state.A = bus->read8(state.HL);
state.HL--;
break;
case 0x0B: // DEC BC
state.BC--;
break;
case 0x1B: // DEC DE
state.DE--;
break;
case 0x2B: // DEC HL
state.HL--;
break;
case 0x3B: // DEC SP
state.SP--;
break;
case 0x0C: // INC C
state.C++;
state.zero = (state.C == 0);
state.subtract = false;
state.halfcarry = (state.C & 0x0F == 0);
break;
case 0x1C: // INC E
state.E++;
state.zero = (state.E == 0);
state.subtract = false;
state.halfcarry = (state.E & 0x0F == 0);
break;
case 0x2C: // INC L
state.L++;
state.zero = (state.L == 0);
state.subtract = false;
state.halfcarry = (state.L & 0x0F == 0);
break;
case 0x3C: // INC A
state.A++;
state.zero = (state.A == 0);
state.subtract = false;
state.halfcarry = (state.A & 0x0F == 0);
break;
case 0x0D: // DEC C
state.C--;
state.zero = (state.C == 0);
state.subtract = true;
state.halfcarry = (state.C & 0x0F == 0x0F);
break;
case 0x1D: // DEC E
state.E--;
state.zero = (state.E == 0);
state.subtract = true;
state.halfcarry = (state.E & 0x0F == 0x0F);
break;
case 0x2D: // DEC L
state.L--;
state.zero = (state.L == 0);
state.subtract = true;
state.halfcarry = (state.L & 0x0F == 0x0F);
break;
case 0x3D: // DEC A
state.A--;
state.zero = (state.A == 0);
state.subtract = true;
state.halfcarry = (state.A & 0x0F == 0x0F);
break;
case 0x0E: // LD C, n8
state.C = readPC8();
mcycles = 2;
break;
case 0x1E: // LD E, n8
state.E = readPC8();
mcycles = 2;
break;
case 0x2E: // LD L, n8
state.L = readPC8();
mcycles = 2;
break;
case 0x3E: // LD A, n8
state.A = readPC8();
mcycles = 2;
break;
case 0x0F: // RRCA
case 0x1F: // RRA
case 0x2F: // CPL
case 0x3F: // CCF
// TODO
break;
}
}
}