|
eabc39590e
|
cpu/panic - Improve declaration
|
2023-08-29 16:51:58 +02:00 |
|
|
216cf660a1
|
cpu/cpu - Add way to signal interrupt from outside
|
2023-08-29 13:45:55 +02:00 |
|
|
7aa1af40fb
|
cpu/cpu - Treat a call to an ISR as a step
|
2023-08-29 13:45:46 +02:00 |
|
|
1fc081b3c5
|
cpu - Fix push operations
|
2023-08-29 12:10:10 +02:00 |
|
|
002b745917
|
cpu - Fix timing of delay when enabling interrupts
|
2023-08-29 12:10:10 +02:00 |
|
|
763fe13f5a
|
decoder - Disable debug printf
|
2023-08-28 23:08:33 +02:00 |
|
|
bd2b577c6c
|
decoder - Add parenthesis to bitwise ANDs
== has priority over & so a & b == c is parsed as a & (b == c)
|
2023-08-28 22:31:52 +02:00 |
|
|
505478b840
|
Improve Cpu class and implement interrupts
|
2023-08-28 21:56:33 +02:00 |
|
|
e4a6b1f9b4
|
decoder - Simplify RST command
We can calculate the rst address directly from the op code.
|
2023-08-28 19:39:18 +02:00 |
|
|
ad2334a6af
|
Implement more parts of decoder
|
2023-08-27 22:19:02 +02:00 |
|
|
93521e559c
|
Simplify decoder code somewhat.
|
2023-08-27 00:15:12 +02:00 |
|
|
ab09bbd9b7
|
more decoder code
|
2023-08-26 23:51:51 +02:00 |
|
|
8d063c08ca
|
Fix build errors.
|
2023-08-26 21:17:47 +02:00 |
|
|
ba5b55a196
|
WIP initial state
|
2023-08-26 19:04:02 +02:00 |
|